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Interface description

JTAG interface connection (20 pin)

There is a standard 20 pin connector defined by ARM. J-Link has a built-in 20-pin JTAG connector, which is compatible with this standard.
JTAG interface connector signals:

Pin	Signal	Type	Description
1	VTref	Input	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2	Vsupply	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.
3	nTRST	Output	JTAG Reset. Output from J-Link to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unin- tentional resets when there is no connection.
5	TDI	Output	JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of target CPU.
7	TMS	Output	JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of target CPU.
9	TCK	Output	JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.
11	RTCK	Input	Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13	TDO	Input	JTAG data output from target CPU. Typically connected to TDO of target CPU.
15	RESET	I/O	Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
17	DBGRQ	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment to be used as a debug request signal to the target system. Typically connected to DBGRQ if available, otherwise left open.
19	5V-Target supply	Output	This pin can be used to supply power to the target hardware.

Notes

All pins marked NC are not connected inside J-Link. Any signal can be applied here; J-Link will simply ignore such a signal.
Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

Pin 2 is not connected inside J-Link. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with J-Link, unless Pin 1 and Pin 2 are connected on the target's JTAG connector.

Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). J-Link will also work if this pin is not connected, but you may experience some limitations when debugging. TRST should be separate from the CPU Reset (pin 15)

Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

Pin 19 (5V-Target supply) of the connector can be used to supply power to the target hardware. Supply volatage is 5V, max. current is 300mA. The output current is monitored and protected agains overload and short-circuit.

SWD and SWO/SWV (also called SWV) compability

SWD overview

The J-Link and J-Trace support ARMs Serial Wire Debug (SWD). SWD replaces the 5-pin JTAG port with a clock (SWDCLK) and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality. SWDIO and SWCLK are overlaid on the TMS and TCK pins. In order to communicate with a SWD device, J-Link sends out data on SWDIO, syn- chronous to the SWCLK. With every rising edge of SWCLK, one bit of data is trans- mitted or received on the SWDIO. The data read from SWDIO can than be retrieved from the input buffer.

SWD connector pinout

The following table shows the SWD pinout:

Pin	Signal	Type	Description
1	VTref	Input	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.
2	Vsupply	NC	This pin is not connected in J-Link. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.
3	Not used	NC	This pin is not used by J-Link. If the device may also be accessed via JTAG, this pin may be connected to nTRST, otherwise leave open.
5	Not used	NC	This pin is not used by J-Link. If the device may also be accessed via JTAG, this pin may be connected to TDI, otherwise leave open.
7	SWDIO	I/O	Single bi-directional data pin.
9	SWCLK	Output	Clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of target CPU.
11	Not used	NC	This pin is not used by J-Link. This pin is not used by J-Link when operating in SWD mode. If the device may also be accessed via JTAG, this pin may be connected to RTCK, otherwise leave open.
13	SWO	Output	Serial Wire Output trace port. (Optional, not required for SWD communication.)
15	RESET	I/O	Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
17	Not used	NC	This pin is not connected in J-Link.
19	5V-Supply	Output	This pin is used to supply power to some eval boards. Not all JLinks supply power on this pin, only the KS (Kickstart) versions. Typically left open on target hardware.

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in J-Link. They should also be connected to GND in the target system.

Serial Wire Output (SWO) overview

J-Link can be used with devices that supports Serial Wire Output (SWO). Serial Wire Output (SWO) support means support for a single pin output signal from the core. It is currently tested with Cortex-M3 only.

Supported SWO speeds

The supported SWO speeds depend on the connected emulator. They can be retrieved from the emulator. Currently, the following are supported:

Emulator	Speed, formula	Resulting max. speed
J-Link V6	6MHz/n, n >= 12	500kHz
J-Link V7	6MHz/n, n >= 1	6MHz

Serial Wire Viewer (SWV) overview

The Instrumentation Trace Macrocell (ITM) and Serial Wire Output (SWO) can be used to form a Serial Wire Viewer (SWV). The Serial Wire Viewer provides a low cost method of obtaining information from inside the MCU. The SWO can output trace data in two output formats, but only one output mechanism is valid at any one time. The 2 defined encodings are UART and Manchester. The current J-Link implementation sup- ports only UART encoding. Serial Wire Viewer uses the SWO pin to transmit different packets for different types of information. The three sources in the Cortex-M3 core which can output information via this pin are:

Instrumentation Trace Macrocell (ITM) for application-driven trace source that supports printf-style debugging. It supports 32 different channels, which allow it to be used for other purposes such as real-time kernel information as well.
Data Watchpoint and Trace (DWT) for real-time variable monitoring and PC-sampling, which can in turn be used to periodically output the PC or various CPU-internal counters, which can be used to obtain profiling information from the target.
Timestamping. Timestamps are emitted relative to packets.

Further application documents

Refer to the following documents for detailed information about SWO/SWV:

Further application documents
CoreSight Components - Technical Reference Manual
Cortex™-M3 - Technical Reference Manual

J-Link Ultra　J-Flash

Documentation download Software download

J-Flash

J-Flash is a PC software running on Windows (Windows 2000 and later) systems, which enables you to program the internal and external flash of your microcontroller via J-Link.

J-Flash comes with sample projects for most popular microcontrollers and eval boards which run out-of-the-box. J-Flash can be controlled via GUI or via command line which makes it also possible to use J-Flash for production purposes.

Features

Works with any ARM7/9/11® and Cortex-M0/M3® core
Supports the following flash devices:
- internal flash of most popular microcontrollers
- CFI-compliant NOR flash (the combinations 18x, 2x8, 1x16, 2x16 are supported)
- most non-CFI compliant NOR flash devices (the combinations 18x, 2x8, 1x16, 2x16 are supported)
- SPI NOR-Flash Read more...
- NAND flash Read more...
- Atmel DataFlash Read more...
Multi-bank programming support*
High speed programming: up to 150 kByte/sec (dep. on flash device)
Very high blank check speed: App. 16 Mybte /sec (depends on target)
Smart read-back: Only non blank-portions of flash transferred and saved
Free 30 day trial version available
Easy to use, comes with projects for standard eval boards

*Currently only supported for Flasher ARM stand-alone mode.

Click to watch demonstration video

Programming speeds

The following table shows some performance values regarding the programming speed.

Microcontroller	Hardware	Flash device	Flash organization	Programming speed (KBytes/sec.)
Atmel AT49BV162A Eval board	Atmel AT91EB40	Atmel AT49BV162A internal flash	1x16 bits	97.8
Atmel AT91RM9200	Cogent CSB337 Eval board	Intel 28F640J3	1x16 bits	93.0
Digi NS9360	Net Silicon NS9360 Eval board	AMD AM29LV160DB	2x16 bits	208.5
Sharp LH7A400-10	LogicPD LH7A400-10 Eval board	Intel 28F640J3A120	2x16 bits	147.8
Analog Devices ADuC7020	Analog Devices ADuC7020 Eval board	Analog Devices ADuC7020 internal flash	1x32 bits	30.8
Atmel AT91SAM7S64	Atmel AT91SAM7-EKS64 Eval board	Atmel AT91SAM7S64 internal flash	1x32 bits	18.5
Atmel AT91SAM7X256	Atmel AT91SAM7X-EK Eval board	Atmel AT91SAM7X256 internal flash	1x32 bits	35.3
Philips LPC2106	IAR LPC2106 Eval board	Philips LPC2106 internal flash	1x32 bits	22.2
ST STR711	IAR STR711 Eval board	ST STR711 internal flash	1x32 bits	50.5
Philips PCF87750	Philips PCF87750 (custom hardware)	Philips PCF87750 internal flash	1x32 bits	68.2

What is multi-bank programming support?

Multi-bank programming support describes the possibility to program different flash devices, present on the same hardware, in one Flash programming session. For example, if you want to use the internal flash of your target hardware as well as the external flash for the target application code, multi-bank programming enables you to download the target application into the internal and external flash in one flash programming session. The settings for both flash banks are saved in the same J-Flash project, so you will only need one project in order to program multiple flash banks.

Support for Atmel DataFlash, NAND flash, SPI-NOR flash

Since the connection of these flashes varies from microcontroller to microcontroller, there are always some modifications which are necessary, to get DataFlash/NAND/SPI-NOR flash supported on a specific hardware.
The J-Flash software comes with sample projects which allow programming the DataFlash/NAND flash on popular eval boards. If you have a hardware-design which is based on the one of the eval board, these sample projects should also work for your custom hardware.
If your hardware design varies too much, usually a custom RAMCode is needed which programs the flash of your target hardware. RAMCodes for custom hardware can be created on request. For more information about pricing and requirements for a custom RAMCode, please contact このメールアドレスはスパムボットから保護されています。閲覧するにはJavaScriptを有効にする必要があります。 . SEGGER also provides a RAMCode template which enables customers to write a custom RAMCode on their own. The RAMCode template is available このメールアドレスはスパムボットから保護されています。閲覧するにはJavaScriptを有効にする必要があります。 .

J-Link Ultra　J-Mem

J-Mem

J-Mem is a small (app. 50 kb) stand-alone application for Microsoft Windows 2000 and Windows XP. It requires a J-Link connected to the USB port and an ARM system connected to J-Link via the JTAG interface.
J-Mem displays memory contents of ARM-systems and allows modifications of RAM and sfrs (Special function registers) while target is running. It makes it possible to look into the memory of an ARM chip at run time; RAM can be modified and sfrs can be written. The type of access for both read and write access can be selected to be 8/16/32 bit.
It works nicely when modifying sfrs, especially because it writes the sfr only after the complete value has been entered.

License & Disclaimer

The program is freeware and can be redistributed without limitation. It is provided free of charge, and, therefore, on an "as is" basis, without warranty of any kind, including - without limitation - the warranties that it is free of defects, merchantable, fit for a particular purpose or non-infringing. The entire risk as to the quality and performance of the software is borne by user.

J-Link Ultra　JTAG Isolator

JTAG Isolator

The J-Link JTAG Isolator can be connected between J-Link and any ARM-board that uses the standard 20-pin JTAG-ARM connector to provide electrical isolation. This is essential when the development tools are not connected to the same ground as the application. It is also useful to protect the development tools from electrical spikes that often occur in some applications, such as motor control applications. Another typical field of application is development of products with sensors or other analog circuitry, in which case the target hardware is protected from electrical noise originating from the development PC.
This product is compatible with J-Link, J-Link Pro and Flasher ARM.

Documentation download

Power supply

Both sides, target and emulator, are totally isolated from each other and separately powered. The target side draws power from pins 1 or 2, the emulator side draws power from pin 19.

Features

1kV DC isolation
3.3V and 5V target operation supported
Powered from emulator and target
JTAG standard 20-pin connection supporting TRST, TDI, TMS, TCK, RTCK, TDO and RESET signals
Power consumption on target side: < 50mA
JTAG frequency: Up to 4MHz
3 LEDs to indicate emulator power, target power and target RESET

Connectors and indicators

The JTAG Isolator uses high speed optocouplers that allow a very low propagation time between input and output. It comes with the following connectors and indicators:

20-pin female EMULATOR connector which can be plugged directly into J-Link
20-pin male TARGET connector for connection of the target cable
Green LED indicating power on the emulator side
Green LED indicating power on the target side
Red LED indicating RESET

Block diagram

The following functional block diagram illustrates the functional connections between the emulator and target.

Target connector

The following picture shows the target side pinout of the J-Link JTAG Isolator:

The Emulator side of the Isolator is plugged directly into the Emulator. The Target side is connected to the target via a 20-pin flat cable.

Pin	Signal	Type	Description
1	VCC	Output	The target side of the isolator draws power over this pin.
2	VCC	Output	The target side of the isolator draws power over this pin.
3	nTRST	Output	JTAG Reset. Output from J-Link to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.
5	TDI	Output	JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.
7	TMS	Output	JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS on target CPU.
9	TCK	Output	JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.
11	RTCK	Input	Return test clock signal from the target. Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and re timed, TCK to dynamically control the TCK rate. J-Link supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.
13	TDO	Input	JTAG data output from target CPU. Typically connected to TDO on target CPU.
15	RESET	I/O	Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".
17	N/C	N/C	This pin is not connected on the target side of the isolator.
19	N/C	N/C	This pin is not connected on the target side of the isolator.

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND.

Using the Isolator with J-Link

In order to use the Isolator, follow these steps:

Plug the Isolator directly into J-Link.
Power J-Link.
Make sure the green LED on the emulator side is lit. If it is not, follow the instruction in the previous section
Connect the target to the target side of the Isolator
If the target is powered, the green LED on the target side should be lit

The red LED on the target side is lit when a Target RESET is active (low).

Preparing J-Link to supply power

J-Link needs to supply 5V power to the emulator side of the adapter on pin 19. In order to do this, you may have to configure J-Link once as follows:

Make sure that SEGGER J-Link software is installed on your machine. It can be downloaded from here
Start J-Link Commander, which can be found under “Start -> Programs -> SEGGER -> J-Link ARM”
Enter the following command: power on perm
Plug in the adapter: The LED on the emulator side should now be lit

Using the Isolator with another ARM emulator

The Isolator has been designed for J-Link, but can also be used with other ARM emulators with the same pin-out. In this case, you should make sure that 5V are supplied to pin 19 of the emulator connector and that your emulator is not damaged when applying 5V to this pin. Do this at your own risk!