パートナー segger-tools NANDナンドフラッシュのサポート
NANDナンドフラッシュのサポート
NAND型フラッシュドライバ
EMFILEは、NANDフラッシュの使用をサポートしています。NANDが点滅するためのオプションのドライバが入手可能です。NANDドライバはほとんどのRAMを必要とする、それは512バイトまたは2バイト（さらに大規模なページのNANDの点滅の小さなセクタ）のセクタサイズで動作し、非常に効率的にできます。ドライバは、1ビットのECCを必要とする1つまたは複数のSLC（シングルレベルセル）NANDの点滅をサポートするよう設計されています。NAND型フラッシュドライバは、ATMELのDataFlashのチップにアクセスするために使用することができます。お使いのシステムでそれを使用するには、フラッシュデバイスにアクセスするための基本的なI / O機能を提供する必要があります。
NANDフラッシュ組織
NANDフラッシュメモリは、アドレスとデータ入力/出力の両方のためだけでなく、コマンド入力用のI / Oピンを利用したシリアルタイプのメモリデバイスです。消去とプログラムの操作が自動的に実行されます。NANDフラッシュデバイス上のデータを格納するために、それは低レベルのフォーマットにする必要があります。
NANDの点滅はブロックの数で構成される。すべてのブロックは、通常、64セクタの数を、含まれています。セクタは、個別に、一度に書き込むことができます。セクターへの書き込み時に、ビットが1から0に書き込むことができます。のみブロック全体（ブロック内のすべてのセクタを）消去することができます。消去は論理1に、ブロックのすべての部門におけるすべてのメモリビットを持ち込むことを意味します。
小型のNANDフラッシュは、（最大256Mバイトまで）（ECC、等）関連情報を格納するためのデータの528バイト、512 + 16の予備バイトのページサイズを持つページへ。大規模なNANDデバイス（256Mバイト以上）は2112バイト、ページに関連する情報を格納するためのデータ+ 64バイトの2048バイトのページサイズを持っている。
例えば、256Mバイトのサイズで標準的なNAND型フラッシュは2112バイトの64セクタ（データは2048バイト+ 64バイトの予備領域）の2048ブロックを持っています。
サポートされるハードウェア
テストおよび互換性のあるNANDの点滅
一般的に、ドライバは、ほぼすべてのシングルレベルセルNANDフラッシュ（SLC）をサポートしています。これは、512 16、2048 64バイトのページサイズを持つNANDの点滅が含まれています。
下の表は、テスト済みまたはテスト済みのデバイスと互換性のあるされているNANDの点滅を示しています。
| メーカー | デバイス | ページのサイズ[バイト] | サイズ[ビット] |
|---|---|---|---|
| ハイニックス | HY27xS08281A HY27xS08561M HY27xS08121M HY27xA081G1M |
512 16 512 16 512 16 512 16 |
16Mx8 32Mx8 64Mx8 128Mx8 |
| サムスン | K9F6408Q0xx K9F6408U0xx K9F2808Q0xx K9F2808U0xx K9F5608Q0xx K9F5608D0xx K9F5608U0xx K9F1208Q0xx K9F1208D0xx K9F1208U0xx K9F1208R0xx K9K1G08R0B K9K1G08B0B K9K1G08U0B K9K1G08U0M K9T1GJ8U0M |
512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 |
8Mx8 8Mx8 16Mx8 16Mx8 32Mx8 32Mx8 32Mx8 64Mx8 64Mx8 64Mx8 64Mx8 128Mx8 128Mx8 128Mx8 128Mx8 128Mx8 |
| ST-Microelectronics | NAND128R3A NAND128W3A NAND256R3A NAND256W3A NAND512R3A NAND512W3A NAND01GR3A NAND01GW3A |
512+16 512+16 512+16 512+16 512+16 512+16 512+16 512+16 |
16Mx8 16Mx8 32Mx8 32Mx8 64Mx8 64Mx8 128Mx8 128Mx8 |
| Toshiba | TC5816BFT TC58V32AFT TC58V64BFTx TC58256AFT TC582562AXB TC58512FTx TH58100FT |
512+16 512+16 512+16 512+16 512+16 512+16 512+16 |
2Mx8 4Mx8 8Mx8 32Mx8 32Mx8 64Mx8 256Mx8 |
| Hynix | HY27UF082G2M HY27UF084G2M HY27UG084G2M HY27UG084GDM |
2048+64 2048+64 2048+64 2048+64 |
256Mx8 512Mx8 512Mx8 512Mx8 |
| Micron | MT29F2G08AAB MT29F2G08ABD MT29F4G08AAA MT29F4G08BAB MT29F2G16AAD |
2048+64 2048+64 2048+64 2048+64 2048+64 |
256Mx8 256Mx8 512Mx8 512Mx8 128Mx16 |
| Samsung | K9F1G08x0A K9F2G08U0M K9K2G08R0A K9K2G08U0M K9F4G08U0M K9F8G08U0M |
2048+64 2048+64 2048+64 2048+64 2048+64 2048+64 |
256Mx8 256Mx8 256Mx8 256Mx8 512Mx8 1024Mx8 |
| ST-Microelectronics | NAND01GR3B NAND01GW3B NAND02GR3B NAND02GW3B NAND04GW3 |
2048+64 2048+64 2048+64 2048+64 2048+64 |
128Mx8 128Mx8 256Mx8 256Mx8 512Mx8 |
Support for devices not in this list
Most other NAND flash devices are compatible with one of the supported devices. Thus the driver can be used with these devices or may only need a little modification, which can be easily done. Get in touch with us, if you have questions about support for devices not in this list.
Tested and compatible DataFlash chips
The NAND flash driver fully supports the ATMEL /DataFlash Cards series up to 32MBit. Currently the following devices are supported:
| Manufacturer | Device |
|---|---|
| ATMEL | AT45DB011B AT45DB021B AT45DB041B AT45DB081B AT45DB161B AT45DB321C AT45BR3214B AT45DCB002 AT45DCB004 |
Pin description - NAND flashes
| Pin | Driver (Device) |
|---|---|
| CE | CHIP ENABLE The CE input enables the device. Signal is active low. If the signal is inactive, device is in standby mode. |
| WE | WRITE ENABLE The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse. |
| RE | READ ENABLE The RE input is the serial data-out control. When active (low) the device outputs data. |
| CLE | COMMAND LATCH ENABLE This pin should be low, when writing commands to the command register. |
| ALE | ADDRESS LATCH ENABLE When active, an address can be written. |
| WP | WRITE PROTECT Typically connected to VCC (recommended), but may also be connected to port pin. |
| R/B | READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or read operation is in process. It returns to high state when the operation is completed. It is an open drain output. Should be connected to a port pin with pull-up. If available a port pin which can trigger an interrupt should be used. |
| I/O0 - I/O7 | DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. |
| I/O8 - I/O15 | DATA INPUTS/OUTPUTS I/O8 - I/O15 16-bit flashes only. |
Pin description - NAND flashes
DataFlash chips are commonly used when low pin count and easy data transfer are required. DataFlash devices use the following pins:
| Pin | Meaning |
|---|---|
| CS | ChipSelect This pin selects the DataFlash device. The device is selected, when CS pin is driven low. |
| SCLK | Serial Clock The SCLK pin is an input-only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCLK and clocked out of the device on the falling edge of SCLK. |
| SI | Serial Data In The SI pin is an input-only pin and is used to transfer data into the device. The SI pin is used for all data input including opcodes and address sequences. |
| SO | Serial Data Out This SO pin is an output pin and is used to transfer data serially out of the device. |
- Data transfer width is 8 bit.
- Chip Select (CS) sets the card active at low-level and inactive at high level.
- Clock signal must be generated by the target system. The serial flash chips are always in slave mode.
- Bit order requires most significant bit (MSB) to be sent out first.
To setup all these requirements, the NAND flash driver will call the function FS_DF_HW_X_Init(), therefore the function FS_DF_HW_X_Init() can be used to initialize the SPI bus.
Theory of operation
NAND flash devices are divided into physical blocks and physical pages. One physical block is the smallest erasable unit; one physical page is the smallest writable unit. Small block NAND flashes contain of multiple pages. One block contain typically 16 / 32 / 64 pages per block. Every page has a size of 528 bytes (512 data bytes + 16 spare bytes). Large block NAND Flash devices contain blocks made up of 64 pages, each page containing 2112 bytes (2048 data bytes + 64 spare bytes). The driver uses the spare bytes for the following reasons:
- To check if the data Status byte and block status are valid. If they are valid the driver uses this sector. When the driver detects a bad sector, the whole block is marked as invalid and its content is copied to a non-defective block.
- To store/read an ECC (Error Correction Code) for data reliability. When reading a sector, the driver also reads the ECC stored in the spare area of the sector, calculates the ECC based on the read data and compares the ECCs. If the ECCs are not identical, the driver tries to recover the data, based on the read ECC. When writing to a page the ECC is calculated based on the data the driver has to write to the page. The calculated ECC is then stored in the spare area.
Error correction code (ECC)
The emFile NAND driver is highly speed optimized and offers a better error detection and correction than a standard memory controller ECC. The ECC is capable of single bit error correction and 2-bit random detection. When a block for which the ECC is computed has 2 or more bit errors, the data cannot be corrected. Standard memory controllers compute an ECC for the complete blocksize (512 / 2048 bytes). The emFile NAND driver computes the ECC for data chunks of 256 bytes (e.g. a page with 2048 bytes is divided into 8 parts of 256 bytes), so the probability to detect and also correct data errors is much higher. This enhancement is realized with a very good performance. The ECC computation of the emFile NAND driver is highly optimized, so that a performance of 18 Mbytes/second can be achieved with a ARM SAM7 running at 48 MHz.
We suggest the use of the the emFile NAND driver without the usage of a memory controller, because the performance of the driver is very high and the error correction is much better if it is controlled from driver side.
Software structure
The NAND Flash driver is split up into different layers, which are shown in the illustration below.
It is possible to use the NAND driver with custom hardware. If port pins or simple memory controller are used to access the flash memory, only the hardware layer needs to be ported, normally no changes to the physical layer are required. If the NAND driver should be used with special memory controller (e.g. special FPGA implementations), the physical layer needs to be adapted. In this case, the hardware layer is not required, because the memory controller manages the hardware access.
Fail-safe operation
The emFile NAND driver is fail-safe. That means that the driver makes only atomic actions and takes the responsibility that the data managed by the file system is always valid. In case of a power loss or a power reset during a write operation, it is always assured that only valid data is stored in the flash. If the power loss interrupts the write operation, the old data will be kept and the block not corrupted.
Wear Leveling
Wear leveling is supported by the driver. Wear leveling makes sure that the number of erase cycles remains approximately equal for each sector. Maximum erase count difference is set to 5. This value specifies a maximum difference of erase counts for different physical sectors before the wear leveling uses the sector with the lowest erase count.