EMVCo - PCD Analog Test
EMVCo - PCDアナログテスト仕様概要
PCD analog test suite EMV CCP
This “Analog debug test suite” is based on:
EMVCo®* Type Approval
Contactless Terminal Level 1
PCD Analogue Test Bench and Test Case Requirements
Version 2.0.1a - November 2010
This analog test suite is compatible with the following tests:
7.8 Performing PCD Test Cases
7.8.1 Radio Frequency Power
7.8.1.1 Verifying the PCD to PICC Power Transfer
7.8.1.2 Verifying the PCD Carrier Frequency
7.8.1.3 Verifying the PCD Operating Field Resetting
7.8.2 PCD to PICC Signal Interface for Type A Communications
7.8.2.1 Verifying the t1 Timing
7.8.2.2 Verifying the Monotonic Decrease from V4 to V2
7.8.2.3 Verifying the Ringing
7.8.2.4 Verifying the t2 Timing
7.8.2.5 Verifying the t4 Timing
7.8.2.6 Verifying the t3 Timing
7.8.2.7 Verifying the Monotonic Increase from V2 to V4
7.8.2.8 Verifying the Overshoot
7.8.3 PICC to PCD Signal Interface for Type A Communications
7.8.3.1 Verifying the Load Modulation VS1,pp at Minimum Modulation
7.8.3.2 Verifying the Load Modulation VS2,pp at Minimum Modulation
7.8.3.3 Verifying the Load Modulation VS1,pp at Maximum Modulation
7.8.3.4 Verifying the Load Modulation VS2,pp at Maximum Modulation
7.8.4 Bit Level Coding Signal Interface for Type A Communications
7.8.4.1 Verifying the PCD Transmitted Bit Rate
7.8.4.2 Verifying the Bit Coding and De-synchronization of PCD to PICC
7.8.4.3 Verifying the Bit Coding and De-synchronization PICC to PCD
7.8.5 PCD to PICC Signal Interface for Type B Communications
7.8.5.1 Verifying the Modulation Index
7.8.5.2 Verifying the Fall Time
7.8.5.3 Verifying the Rise Time
7.8.5.4 Verifying the Monotonic Rising Edge
7.8.5.5 Verifying the Monotonic Falling Edge
7.8.5.6. Verifying Overshoots
7.8.5.7 Verifying Undershoots
7.8.6 PICC to PCD Signal Interface for Type B Communications
7.8.6.1 Verifying the Load Modulation VS1,pp at Minimum Modulation
7.8.6.2 Verifying the Load Modulation VS2,pp at Minimum Modulation
7.8.6.3 Verifying the Load Modulation VS1,pp at Maximum Modulation
7.8.6.4 Verifying the Load Modulation VS2,pp at Maximum Modulation
7.8.7 Bit Level Coding Signal Interface for Type B Communications
7.8.7.1 Verifying the PCD Transmitted Bit Rate
7.8.7.2 Verifying the Synchronization, Bit Coding and de-synchronization of PCD to PICC
7.8.7.3 Verifying the Maximum Limit De-synchronization PICC to PCD (tFSOFF, MAX
7.8.7.4 Verifying the Synchronization, Bit Coding and De-synchronization of PICC to PCD
7.8.7.5 Verifying the Bit Boundaries with Type B Communications
7.8.7.6 Verifying the Minimum Limit De-synchronization PICC to PCD (tFSOFF, MIN)
7-883 Radio Frequency Power and Signal Interface
EMVCo - PCDアナログテスト対応
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