ST MB672
ST MB672
Controller:
- STM32F103ZET6
CPU:
- ARM Cortex-M3
Board main features:
- Three 5V power supply options: Power jack, USB connector or daughter board.
- 128 Mbit serial Flash, 512Kx16 SRAM, 1Gbit NAND Flash and 128 Mbit NOR Flash.
- Boot from User Flash, System memory or SRAM.
- I2S Audio DAC, stereo audio jack.
- 128 MByte MicroSD card.
- Both type A&B Smart card support.
- I2C/SMBus compatible serial interface temperature sensor.
- 2 channels of RS232 communication with RTS/CTS handshake support on one channel.
- IrDA transceiver.
- USB2.0 full speed connection.
- CAN2.0A/B compliant connection.
- Inductor Motor Control connector.
- JTAG and Trace Debug support.
- 240x320 TFT color LCD
- Joystick with 4-direction control and selector.
- Reset, Wakeup, Tamper and User button.
- 4 LEDs.
- RTC with backup battery.
- Extension connector for daughter board or wrapping board.
Controller main features:
- Implements the ARM architecture v7-M
- Thumb-2 instruction set (Enhanced levels of performance, energy efficiency, code density, mixed mode capability, ARM levels of performance with Thumb level code density)
- Memory Protection Unit (MPU)
- Embedded Trace Macrocell(ETM)
- Data Watchpoint and Trace unit (DWT)
- Flash Patch and Breakpoint unit (FPB)
- Debug Port (SW-DP or SWJ-DP)
- Single cycle multiply and hardware divide instructions
- Preconfigured memory map
- Up to 4 gigabytes of addressable memory space
- Predefined addresses for code, memory, external devices, peripherals
- Dedicated space for vendor specific addressability
- Atomic bit manipulation with bit banding (Direct access to single bits of data)
- Unaligned data storage and access
- Integrated sleep modes (Sleep Now, Sleep on Exit)
Available software:
Subscribe to ST MB672 eval software notification 
J-Trace for Cortex-M3
J-Trace for Cortex-M3 JTAG emulator with trace support for Cortex-M3 cores
J-Trace for Cortex-M3 is a JTAG emulator designed for Cortex-M3 cores which includes trace (ETM) support. J-Trace for Cortex-M3 can also be used as a J-Link and it also supports ARM7/9 cores. Tracing on ARM7/9 targets is not supported.
Features
- Has all the J-Link functionality
- Hi-Speed-USB 2.0 interface
- Supports tracing on Cortex-M3 targets
- 4 MB trace buffer
19-pin JTAG/SWD and Trace connector
J-Trace provides a JTAG/SWD+Trace connector. This connector is a 19-pin connector. It connects to the target via an 1-1 cable. The following table lists the J-Link / J-Trace SWD pinout.
| Pin | Signal | Type | Description |
|---|---|---|---|
| 1 | VTref | Input | This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor. |
| 2 | SWDIO/ TMS | I/O / output | JTAG mode set input of target CPU. This pin should be pulled up on the target. Typically connected to TMS of the target CPU. |
| 4 | SWCLK/TCK | Output | JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Typically connected to TCK of the target CPU. |
| 6 | SWO / TDO | Input | JTAG data output from target CPU. Typically connected to TDO of the target CPU. |
| --- | --- | --- | This pin (normally pin 7) is not existent on the 19-pin JTAG/SWD and Trace connector. |
| 8 | TDI | Output | JTAG data input of target CPU.- It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI of the target CPU. |
| 9 | NC | NC | Not connected inside J-Link. Leave open on target hardware. |
| 10 | nRESET | I/O | Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET". |
| 11 | 5V-Supply | Output | This pin can be used to supply power to the target hardware. For more information about how to enable/disable the power supply, please refer to Target power supply on page 142. |
| 12 | TRACECLK | Input | Input trace clock. Trace clock = 1/2 CPU clock. |
| 13 | 5V-Supply | Output | This pin can be used to supply power to the target hardware. For more information about how to enable/disable the power supply, please refer to Target power supply on page 142. |
| 14 | TRACEDATA[0] | Input | Input Trace data pin 0. |
| 16 | TRACEDATA[1] | Input | Input Trace data pin 1. |
| 18 | TRACEDATA[2] | Input | Input Trace data pin 2. |
| 20 | TRACEDATA[3] | Input | Input Trace data pin 3. |
Specifications
| General | |
|---|---|
| Supported OS |
Microsoft Windows 2000 Microsoft Windows XP Microsoft Windows XP x64 Microsoft Windows 2003 Microsoft Windows 2003 x64 Microsoft Windows Vista Microsoft Windows Vista x64 Windows 7 Windows 7 x64 |
| Electromagnetic compatibility (EMC) | EN 55022, EN 55024 |
| Operating temperature | +5°C ... +60°C |
| Storage temperature | -20°C ... +65 °C |
| Relative humidity (non-condensing) | Max. 90% rH |
| Size (without cables) | 123mm x 68mm x 30mm |
| Weight | (without cables) 120g |
| Mechanical | |
| USB interface | USB 2.0, Hi-Speed |
| Target interface | JTAG/SWD 20-pin (14-pin adapter available) JTAG/SWD + Trace 19-pin |
| JTAG/SWD Interface, Electrical | |
| Power supply | USB powered Max. 50mA + Target Supply current. |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Target supply voltage | 4.5V ... 5V (if powered with 5V on USB) |
| Target supply current | Max. 300mA |
| LOW level input voltage (VIL) | Max. 40% of VIF |
| HIGH level input voltage (VIH) | Min. 60% of VIF |
| JTAG/SWD Interface, Timing | |
| Data input rise time (Trdi) | Max. 20ns |
| Data input fall time (Tfdi) | Max. 20ns |
| Data output rise time (Trdo) | Max. 10ns |
| Data output fall time (Tfdo) | Max. 10ns |
| Clock rise time (Trc) | Max. 10ns |
| Clock fall time (Tfc) | Max. 10ns |
| Trace Interface, Electrical | |
| Power supply | USB powered Max. 50mA + Target Supply current. |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Voltage interface low pulse (VIL) | Max. 40% of VIF |
| Voltage interface high pulse (VIH) | Min. 60% of VIF |
| Trace Interface, Timing | |
| TRACECLK low pulse width (Twl) | Min. 2ns |
| TRACECLK high pulse width (Twh) | Min. 2ns |
| Data rise time (Trd) | Max. 3ns |
| Data fall time (Tfd) | Max. 3ns |
| Clock rise time (Trc) | Max. 3ns |
| Clock fall time (Tfc) | Max. 3ns |
| Data setup time (Ts) | Min. 3ns |
| Data hold time (Th) | Min. 2ns |
J-Link ColdFire IAR Integration
IAR Integration
J-Link does not work with IAR compiler versions older than 3.40.
In order to use J-Link with the 4.41 Version install the USB driver first. After that, start the workbench:
- left-click on the the project in the project window.
- Select Project|Options from the menu and you will see the following:
- Click on Debugger and select "J-Link/J-Trace" in the listbox:
- Clicking "J-Link/J-Trace" will show addtitional options for J-Link:
Now you are ready to go
You should be able to start debugging and use J-Link. Please note that most ARM cores require a macro file to be executed before debugging can start; this macro file typically initializes certain parts of the ARM chip (memory access) that are required for the RAM to function.
Supported command line switches
armjlink.dll currently supports the following command line switches:
--drv_communication_log // Standard option (Checkmark in the dialog box)
--jlink_no_reset_at_startup [0/1]
--jlink_reset_pulls_trst [0/1]
--jlink_reset_pulls_reset [0/1]
--jlink_speed [30..8000] // kHz
--jlink_device_select [0..n] // Support for multi core debugging
Texas Instruments (Luminary)
Texas Instruments (Luminary Micro) Eval boards
We have board support packages (BSPs) and complete projects available for various Luminary Micro Eval boards.
Different software packages are available for different boards; the packages include some or all of the following components:
- embOS - real time OS / RTOS
- emWin - graphic software / GUI
- emFile - file system with support for NAND-, NOR- flashes, SD, CF cards, IDE and more
- emUSB - USB device stack with support for bulk, MSD, CDC, HID and more
Some packages are executable demos, which can not be modified; some packages are trial versions, which come with the software in a library and the application in source code form, as well as a project for the IDE that has been used. Trial versions can usually be recompiled easily in less than a minute if the required compiler and IDE is installed. The application program can be modified, allowing intensive tests of the software. emWin trial versions usually also contain a simulation environment which allows test and recompilation on a PC.
Below is a list of supported Eval boards. The software can easily be ported to other hardware platforms. If you are looking for software for an Eval board not in this list, please get in touch with us.
Supported Eval boards
Luminary LM3S1968
Controller:
- LM3S1968
CPU:
- ARM Cortex-M3
Board main features:
- Support for battery-backed hibernate mode
- OLED graphics display with 128 x 96 pixel resolution
- User LED, navigation switches, and select pushbuttons
- Magnetic speaker
- LM3S1968 I/O available on labeled break-out pads
- Standard ARM® 20-pin JTAG debug connector with input and output modes
Luminary LM3S2965 CAN
Controller:
- LM3S2965
CPU:
- ARM Cortex-M3
Board main features:
- Fully operational CAN Network-in-a-box
- 128x64 pixel 16-shade monochromatic OLED display
- User-programmable push buttons and LED
- Magnetic speaker
- Convenient reset push button and power indicator LED
- Serial in-circuit debug interface over USB
- Powered over USB with included USB cable
- Break-out pads for all LM3S2965 I/O
Luminary LM3S3748 EVB
Controller:
- LM3S3748
CPU:
- ARM Cortex-M3
Board main features:
- 128x128 CSTN LCD graphics display
- USB host connector
- MiniUSB device connector
- External +3.3V power supply
- 2 channel oscilloscope
- MicroSD card slot
- 3 status LEDs
- Reset push button
- Debugger USB interface
- JTAG/SWD connector
Luminary LM3S6965 Ethernet
Controller:
- LM3S6965
CPU:
- ARM Cortex-M3
Board main features:
- 10/100 Ethernet
- Simple setup: USB cable provides serial communication, debugging, and power
- OLED graphics display with 128 x 64 pixel resolution and 16 shades of gray
- User LED, navigation switches, and select pushbuttons
- Magnetic speaker
- All LM3S6965 I/O available on labeled break-out pads
- Standard ARM® 20-pin JTAG debug connector with input and output modes
- microSD card slot
Luminary LM3S8962
Controller:
- LM3S8962
CPU:
- ARM-Cortex M3
Board main features:
- fully-integrated 10/100 embedded Ethernet controller
- OLED graphics display with 128 x 96 pixel resolution
- User LED, navigation switches, and select pushbuttons
- Magnetic speaker
- LM3S8962 I/O available on labeled break-out pads
- Standard ARM® 20-pin JTAG debug connector with input and output modes
- Standalone CAN device board using Stellaris LM3S2110 microcontroller
Luminary LM3S9B90
Controller:
- LM3S9B90
CPU:
- ARM-Cortex M3
Board main features:
- fully-integrated 10/100 embedded Ethernet controller
- USB 2.0 Full-Speed OTG port
- Virtual serial communications port capability
- Oversized board pads for GPIO access
- Reset pushbutton and power LED
- User pushbutton and LED
Luminary LM3S9B96
Controller:
- LM3S9B96
CPU:
- ARM-Coretx M3
Board main features:
- LCD Display with Touch
- Ethernet controller
- Reset pushbutton and power LED
- User pushbutton and LED
- USB Connector
- Ethernet Connector
IAR TMS470R1B1M
IAR TMS470R1B1M
Controller:
- TMS470R1B1M (TI)
CPU:
- ARM7TDMI
Board main features:
- TMS470R1B1M processor
- 1M-Byte Flash Program Memory
- 64K-Byte Static RAM
- 60-MHz System Clock
- High-End Timer with 12 Programmable I/O Channels
- 10-Bit, 12-Input Multi-buffered Analog-to-Digital Converter
- Potentiometer and thermistor wired to ADC 2 SPI
- 3 SCI, 2 ported to RS232 connectors
- 2 High-End CAN Controllers
- 5 I2C
- 32 character LCD Display
- 5 push buttons
- 16 user LEDs
- 20x20 prototyping area
- Supports 8- and 16-Bit Expansion Bus with 42 I/O Expansion Bus Pins
- Memory Security Module (MSM)
- JTAG Security Module
- Direct Memory Access (DMA) Controller - 32 Control Packets and 16 Channels
- Schematics included
- RoHS compliant
Controller main features:
- 32/16-bit RISC architecture (ARM v4T)
- 32-bit ARM instruction set for maximum performance and flexibility
- 16-bit Thumb instruction set for increased code density
- Unified bus interface, 32-bit data bus carries both instructions and data
- Three-stage pipeline
- 32-bit ALU
- Very small die size and low power consumption
- Coprocessor interface
- EmbeddedICE-RT real-time debug unit
- JTAG interface unit
- Interface for direct connection to Embedded Trace Macrocell (ETM)